Lowest power chipset-world record set by Silicon
Line
[Jan
22]MUNICH, Germany-- Silicon
Line GmbH, a German fabless analog IC company, today announced
the release of a 2.5 Gigabit per second (Gb/s) chipset comprising
a transimpedance amplifier (TIA) with integrated limiting amplifier
and a Vertical Cavity Surface Emitting Laser (VCSEL) driver.
Photo:Silicon Line's World-Record: 2.5 Gb/s Optical
Link Consuming Less Than 10 mW.
Silicon Line GmbH introduces an ultra-low power physical layer chipset
for optical data transmission
Image: Silicon Line's
PHY-Layer Chipset
(enlarge
photo)
The complete chipset exhibits a total power dissipation of below
10 mW, only.
This power number includes all necessary
currents through the laser as well as the power dissipated by the
resistive output load connected to the TIA. The own power need of
the VCSEL driver (SL82026) itself is far below 1 mW and that of
the transimpedance amplifier (SL82016) far below 5 mW.
“Optical data transmission based on polymer optical
fibers or waveguides becomes more and more prevalent.” said Holger
Hoeltke, Managing Director at Silicon
Line.
"Especially in mobile or portable electronics, where
massive EMI-constrains, bandwidth requirements and mechanical issues
challenge the traditional physical layer design, ultra-low power
optical data transmission comes in as perfect alternative. With
its PHY-layer chipset Silicon Line provides an enabling technology
into these markets."
The chipset SL82016 / SL82026 features sub-LVDS
I/Os, which provide a differential output voltage of 200 mV. Upon
request, Silicon Line provides to its VCSEL-driver a temperature
controller, which automatically maintains over a wide temperature
range a given extinction ratio for the VCSEL. Silicon
Line's TIA, the SL82016, works together with either a GaAs
photodiode or a Si photodiode.
With a minimum input current of 20 µApp, the
SL82016 allows for an optical input sensitivity of -16 dBm at a
BER of 10-12 at 2.5 Gbps.
"Due to their excellent power efficiency, both
chips may also be used for parallel optical links." said Martin
Groepl, Silicon
Line's Technical Director. "With only a few adaptations
we may provide them as one-dimensional or two-dimensional arrays.
With that they're suitable for high-speed board-to-board, backplane
or chip-to-chip connections."
The SL82016 as well as the SL82026 exhibit a
chip area of less than 0.5 mm˛. Both ICs are available in bare die
form. Sampling of the ICs starts now.